1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a plurality of macro cells on the same chip, and more particularly, to a semiconductor integrated circuit permitting selective testing of such macro cells.
2. Description of the Prior Art
In a semiconductor integrated circuit having a plurality of macro cells on the same chip, testing such as operation verification is sometimes required for each macro cell. As a semiconductor integrated circuit permitting such testing, known is one that receives a predetermined coded selection signal externally, decodes the signal internally and selectively brings each macro cell to a test operation state based on the decoded signal (see Japanese Laid-Open Patent Publication No. 1-195379, for example).
In receiving a selection signal from outside the semiconductor integrated circuit as described above, when one macro cell is to be selected among a total of the n-th power of 2 macro cells, for example, at least n external signal input terminals will be necessary. If two or more macro cells are to be made selectable simultaneously, a further larger number of terminals will be necessary.
The conventional semiconductor integrated circuit therefore has a problem that neither reduction in the number of terminals nor enhancement in flexibility of testing is available.